1. Field of the Invention
The present invention relates in general to a failure detection system which performs failure detection of an integrated circuit, and more particularly to a failure detection system which is capable of performing dynamic failure detection of the integrated circuit when high reliability is required of the integrated circuit.
2. Description of the Background Art
Generally, it is not easy for an apparatus to make a judgment whether or not an integrated circuit included therein always performs a normal operation. In other words, the surroundings such as temperature, electric field, magnetic field, electromagnetic radiation and density of radioactive rays change dynamically, so that it is difficult to check if the apparatus is disposed in such surroundings as ensure a normal operation for the apparatus. As to malfunction of the integrated circuit, which is one of major factors to cause malfunction of the apparatus, it generally has great difficulty to be detected without special measures. Thus, there arises a need of failure detection of the integrated circuit by employing a failure detection system, and thus the failure detection system therefore is disclosed in Japanese Patent Application Laid Open Gazette 1-193942 and the like.
Referring to FIGS. 14 to 19, a conventional failure detection system will be described. FIG. 14 illustrates a configuration of an apparatus including an integrated circuit. In FIG. 14, reference numerals 101 and 102 denote devices including integrated circuits with different functions, and numeral 103 denotes a central processing unit (hereinafter referred to as "CPU") which controls the devices 101 and 102. Reference numeral 104 denotes a control signal bus for transmitting control signals such as read/write signal, chip enable signal and self-test enable signal, reference numeral 105 denotes a data signal bus for transmitting data signals and numeral 106 denotes an address signal bus for transmitting address signals.
In the apparatus of FIG. 14, the devices 101 and 102 comprise failure detection circuits 101a and 102a, respectively, to detect failure of the integrated circuits incorporated therein. The CPU 103 performs control operations associated with read/write, self-test and the like through the control signal bus 104, the data signal bus 105 and the address signal bus 106. Moreover, the devices 101 and 102 perform error check of the respective integrated circuits by self-test.
FIG. 15 is a block diagram showing, e.g., a configuration of the conventional failure detection circuit 101a. In FIG. 15, reference numeral 1 denotes an input signal conductor disposed within the integrated circuit so as to transmit data to a function (e.g., an ALU in a microprocessor) in the integrated circuit (e.g., a microprocessor). Reference numeral 2 denotes a random logic unit (functional block) provided within the integrated circuit for performing a predetermined function in response to the data inputted thereto through the input signal conductor 1, and numeral 3 denotes an output signal conductor for outputting a result of logical operation and the like given by the random logic unit 2 to other functions within the integrated circuit or to the outside thereof. The input signal conductor 1 and the output signal conductor 3 usually have a plurality of lines, respectively, corresponding to the number of bits of the signal.
Reference numeral 4 denotes a test comparison ROM for storing expected data to be outputted in response to the input of the random logic unit 2. Reference numeral 5 denotes a ROM address generating unit for generating an address of the test comparison ROM 4 when the self-test is conducted. Reference numeral 6 denotes a comparator for comparing an output from the random logic unit 2 with a pattern stored in the test comparison ROM 4, to output a signal indicating agreement or disagreement to a signal conductor 11.
Reference numeral 22 denotes a test pattern ROM for storing an input pattern used for the self-test in the failure detection circuit 101a and outputting the test pattern to a signal conductor 23 according to an address signal which is generated in the ROM address generating unit 5 and then delivered through a signal conductor 24. Reference numeral 30 denotes a selector which receives a signal delivered through the signal conductor 23 and a signal delivered through the input signal conductor 1, and then outputs either of the signal delivered through the signal conductor 23 and the signal delivered through the input signal conductor 1 in response to the enable signal and the self-test enable signal applied respectively through signal conductors 28 and 29 to a signal conductor 25 connected to the random logic unit 2. Reference numeral 27 denotes a switch for making a choice whether or not to transmit an output signal applied from the random logic unit 2 through a signal conductor 26 to the output signal conductor 3.
FIG. 16 shows an exemplary configuration of the selector 30. In FIG. 16, L1 denotes an invertor for outputting the inverted logic of the enable signal inputted through the signal conductor 28. L2 denotes an OR gate having two inputs for receiving the enable signal and the self-test enable signal by the two inputs through the signal conductors 28 and 29 respectively. L3 denotes an AND gate having three inputs for receiving an output from the invertor L1, the input pattern for the self-test delivered through the signal conductor 23 and an output from the OR gate L2 by the three inputs, respectively. L4 denotes an AND gate having two inputs for receiving an input signal delivered through the input signal conductor 1 and the enable signal delivered through the signal conductor 28 by the two inputs, respectively. L5 denotes an OR gate for taking a logical sum of outputs from the And gates L3 and L4 to output it. Reference numerals 30a to 30d denote selectors for one bit and each have the same circuit configuration so as to selectively output one bit of the input signal delivered through the input signal conductor 1 or one bit of the input pattern delivered through the signal conductor 23. The selector 30a, for example, consists of the AND gates L3 and L4 and the OR gate L5.
The operation of the selector 30 will be described. When the enable signal applied through the signal conductor 28 is at high level, at least one of the three inputs of the AND gate L3 takes low level and one of the two inputs of the AND gate L4 takes high level, so that the selector 30 always applies the signal of the input signal conductor 1 to the signal conductor 25.
On the other hand, when the enable signal is at low level, if the self-test enable signal applied through the signal conductor 29 is at high level, the selector 30 applies the signal of the signal conductor 23 to the signal conductor 25, and otherwise outputs a signal of low level to the signal conductor 25.
Next, FIG. 17 shows an exemplary configuration of the switch 27. The switch 27 consists of a plurality of AND gates L61 to L63 each having two inputs and taking one bit out of the signal of the signal conductor 28 by one input and one bit out of the output signal from the random logic unit 2 corresponding to the enable signal by the other input. Thus, the signal conductor 26 transmits the output signal from the random logic unit 2 of FIG. 15 and is connected to the input of the switch 27. Outputs of the AND gates L61 to L64 are connected to the output signal conductor 3. When the enable signal delivered through the signal conductor 28 is at high level, the switch 27 transmits the signal applied through the signal conductor 26 connected to the random logic unit 2 to the output signal conductor 3 and otherwise outputs a signal of low level to the output signal conductor 3.
The operation of the failure detection circuit 101a will be described. The random logic unit 2 processes the signal of the input signal conductor 1 to output the processed result to the output signal conductor 3. It is assumed that the output is uniquely determined depending on the input. The integrated circuit including the random logic unit 2 carries out an operation by reading out the processed result of the random logic unit 2, which is obtained in response to the data inputted thereto through the input signal conductor 1, through the output signal conductor 3.
The integrated circuit is intermittently used by the CPU 103 which is disposed outside and connected to the device 101 incorporating the integrated circuit therein. FIG. 18 is a timing chart showing the states. As can be seen from the figure, the enable signal periodically attains low level. While the enable signal is low level, the self-test enable signal attains high level. While the CPU 103 uses the integrated circuit, the signal conductor 28 keeps high level. Accordingly, the selector 30 transmits the signal of the input signal conductor 1 to the random logic unit 2, and the switch 27 outputs the processed result of the random logic unit 2 to the output signal conductor 3. In this case, the integrated circuit carries out a normal operation without conducting the self-test.
When the enable signal is at low level and the self-enable signal is at high level, the integrated circuit performs the self-test instead of normal operation. The failure detection circuit 101a carries out the following process in order to check if the random logic unit 2 outputs a proper output in response to an input.
When the enable signal is at low level and the self-test enable signal is at low level, the selector 30 outputs a signal of low level to the signal conductor 25. When the enable signal is at low level and the self-test enable signal is at high level, the ROM address generating unit 5 generates the address signal of the test comparison ROM 4 to output it to the signal conductor 9 and signal conductor 24. The address signal is inputted through the signal conductor 24 to the test pattern ROM 22, and then one of the input patterns stored in the test pattern ROM 22 is outputted to the signal conductor 23. At the same time, the test comparison ROM 4 outputs an expected pattern corresponding to the address signal inputted through the signal conductor 9, i.e., the input pattern outputted from the test pattern ROM 22, to a signal conductor 10. Since the selector 30 transmits the signal of the signal conductor 23 to the signal conductor 25, the output from the test pattern ROM 22 is inputted to the random logic unit 2 and then the processed result of the random logic unit 2 is outputted to the signal conductor 26. The comparator 6 receives the processed result and the expected pattern, and compares these two signals to output a signal indicating agreement or disagreement outside through the signal conductor 11.
In the above-mentioned failure detection system, the self-test may be performed immediately after the integrated circuit is reset. Furthermore, in the case that the apparatus always or for long time uses the integrated circuit exclusively, there may be an arrangement where a timer provided within the integrated circuit applies a self-test request signal to the outside CPU 103 after the lapse of a certain period so that the apparatus can periodically start the self-test of the integrated circuit.
In the conventional failure detection system, if the random logic unit 2 includes a register, data in the register are saved temporarily in a memory just before the self-test is started, and then data for the self-test are loaded in the register to conduct the self-test. After the self-test, the saved data are restored from the temporary memory to the register to perform an ordinary operation.
When the random logic unit 2 processes data under control of the CPU 103, such a configuration as shown in FIG. 19 makes it possible to start the self-test by interruption.
In FIG. 19, reference numeral 2a denotes a random logic for performing a logical operation within the random logic unit 2, 2b denotes a register for temporarily storing the data inputted to the random logic 2a from the outside through the signal conductor 25, and 2c denotes a register for temporarily storing the data processed in the random logic 2a to be outputted through the signal conductor 26. Reference numeral 31 denotes an address signal bus for transmitting an address signal indicating where the data are delivered from the registers 2b and 2c and a memory, and numeral 32 denotes a read/write signal bus for transmitting a read/write signal directing the registers 2b and 2c and the memory to turn into whether read-out mode or write mode.
Reference numeral 33 denotes the memory for saving the data stored in the registers 2b and 2c when the self-test is conducted and numeral 34 denotes a data bus provided within the integrated circuit, for transmitting the data stored in the registers 2b and 2c to the memory 33 and transmitting the data stored in the memory 33 to the registers 2b and 2c.
Reference numeral 35 denotes a timer provided within the integrated circuit, which counts down in synchronization with clocks CLK inputted thereto, and after the lapse of predetermined period, outputs an interrupt signal INT from the signal conductor 36 through the control bus 104 to the CPU 103 shown in FIG. 14 so that the random logic unit 2 may start the self-test periodically.
When the timer 35 receives a signal indicating an end of the self-test from the ROM address generating unit 5 through a signal conductor 37, it reads out the value stored in a reload register 38 and starts again counting down in synchronization with the clocks CLK. After the lapse of predetermined period, the timer outputs the interrupt signal INT to the CPU 103 shown in FIG. 13 from the signal conductor 36 through the control signal bus 104 of FIG. 14.
When the CPU 103 receives the interrupt signal INT, it makes the signal conductor 28 low level to release the device 101 from which the interrupt signal has been outputted. The CPU 103 makes the signal conductor 29 high level. The device 101 conducts the self-test while being released.
The read/write signal is switched so that the data stored in the registers 2b and 2c should be outputted to the data bus 34. Accordingly, the data which have not been processed yet by the random logic 2a are outputted from the register 2b through the data bus 34 to be stored in the memory 33 at a predetermined, for example, address 33a, while the data which have been processed by the random logic 2a, i.e., which have not been processed by other parts of the integrated circuit are outputted from the register 2c through the data bus 34 to be stored in the memory 33 at, for example, an address 33b.
When the signal conductor 28 becomes low level and the signal conductor 29 becomes high level at the same time, the selector 30 is switched so that the signal conductors 23 and 25 should be connected to each other. The ROM address generating unit 5 outputs the address signal to the test comparison ROM 4 and the test pattern ROM 22 in sequence through the signal conductors 9 and 24 respectively, and then the test pattern ROM 22 outputs the input pattern corresponding to the address signal through the signal conductor 23 to the random logic unit 2, while the test comparison ROM 4 outputs the expected data through the signal conductor 10 to the comparator 6. The comparator 6 compares the data processed by the random logic unit 2 with the expected data and then outputs the comparison result of agreement or disagreement through the signal conductor 11.
At the end of the self-test, the ROM address generating unit 5 outputs a signal indicating the end of the self-test to the timer 35 and the CPU 103 of FIG. 14 through the signal conductor 37. The timer 35 is thereby initialized and then begins to measure the time in order to start the next self-test. The CPU 103 makes the signal conductor 29 low level.
When the signal conductor 29 becomes low level and thus the self-test is completed, the CPU 103 outputs the address signal and the read/write signal through the address bus 31 and the read/write signal bus 32, respectively, so that the data of the memory 33 which have been stored in the registers 2b and 2c before the self-test can be restored. At the time when the data are restored in the registers 2b and 2c, the CPU 103 starts operation again by making the enable signal high level.
Next, when the CPU 103 makes the signal conductor 28 high level, the selector 30 connects the input signal conductor 1 to the signal conductor 25 and then the switch 27 turns on, thereby turning the random logic unit 2 into ordinary data processing mode.
The conventional failure detection system having the foregoing arrangement has the problem that it can not respond the variation of error occurrence ratio of input patterns depending on the conditions under which it is used and therefore can not accomplish a self-test of high error detection ratio because the failure detection system performs a dynamic error detection by using fixed input patterns stored in the test pattern ROM 22.
Moreover, there is another problem that it is impossible to check if the failure detection system which conducts the self-test has malfunction.